And here it is, on the right, with the added pnp transistor to speed up the turn on of the npn output transistor and the turn off of the pnp output transistor.
As before, capacitor C1 represents the gate of a p- mosfet power switch.
As with the Cuk version, its base is driven via a capacitor with a diode to stop the capacitor just charging to the rail voltage and taking no further part in proceedings.
With a turn off transistor installed, R3, the resistor that used to do the job now done by Q4 can be increased to reduce overall power consumption, and R4 can be a low value as it is only used briefly each cycle.
R5 is only there to help me measure current consumption from the V2 power source, but in a real circuit it would help to isolate much of the circit from the few-amp switching transients in and out of C1.
One not so great thing about this scheme, is that (unless C2 is low enough) both transistors are briefly on together (when Q3 is turning on and Q4 turning off), but R4 limits current flow – to 45mA in this case.
As with the Cuk circuit, resistor and capacitor values all need tuning to work with the available input signal rails, and to get the speed you need at minimal power consumption.
It is worth noting that, in this circuit, the mosfet’s base gets pulled down close to 0V, which might put unnecessary strain onto it.
The original circuit, needing a wasteful low value for R3
An bootstrapped version with an n-channel switching fet would probably be a better bet in the end, but it would sacrifice the ability to operate at 100% duty cycle.
Circuit diagrams drawn and simulated using LTspice – thanks to ADI for keeping LTspice free